Integrated circuit devices that support high data bandwidth may suffer from simultaneous switching noise (SSN), particularly when switching a plurality of output pins or driving groups of parallel signal lines (e.g., buses) at high frequency. Conventional techniques to reduce SSN have included the use of data inversion circuits that operate to limit the number of parallel data signals that switch value during consecutive data output cycles. For example, FIG. 1 illustrates a conventional data inversion circuit 10 that includes an input XOR circuit 11, a data comparator 13 and an output XOR circuit 12. The input XOR circuit 11 receives a plurality of current input signals FDO1–FDO8 and a plurality of prior output signals DO1–DO8, which are fed back from parallel output pins of the data inversion circuit 10. The XOR logic gates within the input XOR circuit 11 generate a plurality of signals that are provided to inputs of the data comparator 13. This data comparator 13 is configured to generate a single flag signal (FLG) having a logic value equal to 1 whenever a number of bit differences (Δ) between the data pairs (FDO1, DO1), (FDO2, DO2), (FD31, DO3), (FDO4, DO4), (FDO5, DO5), (FDO6, DO6), (FDO7, DO7) and (FDO8, DO8) is greater than or equal to four (4). This flag signal may also be referred to as a parity signal (S). Thus, if the prior value of DO1–DO8=[00000000] and the new value of FDO1–FDO8=[11111110], then the flag signal FLG will have a value of 1 because Δ=7. In this case, the new output signals DO1–DO8 will equal [00000001], which means that only one of the output pins will switch value between the old and new output signals. The flag signal FLG will also be provided as an output of the data inversion circuit 10 so that the circuit or device receiving the output signals can properly interpret their values. In contrast, if the prior value of DO1–DO8=[00001111] and the new value of FDO1–FDO8=[00000001], then the flag signal FLG will have a value of 0 because Δ=3. In this case, no data inversion operation will be performed by the output XOR circuit 12 and the new output signals DO1–DO8 will be generated as [00000001].
As will be understood by those skilled in the art, the receipt of this flag signal FLG at the inputs of the NOR gates within the output XOR circuit 12 may be delayed relative to the leading edges of the current input signals FDO1–FDO8, which are evaluated when determining the value of the flag signal FLG. In particular, a sum of the timing delays generated by the input XOR circuit 11 and the data comparator 13 may equal the delay between the leading edges of the current input signals FDO1–FDO8 and the leading edge of the flag signal FLG received by the output XOR circuit 12. This delay may operate to reduce the width of the data valid window that is present at the outputs of the output XOR circuit 12 and thereby reduce a maximum operating frequency of the data inversion circuit 10.
Another conventional technique for reducing SSN in integrated circuits that output parallel signals to a data bus is disclosed in U.S. Pat. No. 5,931,927 to Takashima. In particular, FIG. 3 of the '927 patent illustrates an input/output device that generates an m-bit data signal and a single bit parity signal to a bus. Half of the m-bit data signal may be inverted if necessary to make the number of “1” signal values more nearly equivalent to the number of “0” signal values that are generated during an output cycle. In particular, the '927 patent shows a Circuit A (left side) and a Circuit A (right side), with each circuit receiving ½ m bits of data. If the Circuit A (left side) and the Circuit A (right side) all receive logic 1 signals, then the parity outputs from the two circuits will be equal to “1”, which reflects the fact that more “1s” than “0s” are present. When this occurs, a data inversion flag, which is generated by an exclusive XNOR gate, will be set to a logic 1 value. When the data inversion flag is set to a logic 1 value, then the outputs of the Circuit A (right side) will be inverted by the data inversion circuit. Accordingly, the output buffer (left side) will receive all “1s” from the Circuit A (left side) and the output buffer (right side) will receive all “0s” from the data inversion circuit. A single-bit output buffer will also generate a flag signal (F1) so that the inversion of the data from the Circuit A (right side) can be properly interpreted once the data is passed to the bus.
Thus, in FIG. 3 of the '927 patent, if the m-bit data signal provided to circuit A (left side) and circuit A (right side) during a first cycle is: 11111000 and 00000111 and the m-bit data signal provided during a second cycle is: 00000111 and 11111000, then the data inversion flag will not be set and the m-bit data provided to the bus during consecutive cycles will be:
1st cycle:1111100000000111↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓2nd cycle:0000011111111000Δ = 16
Thus, using the circuit of FIG. 3 of the '927 patent, the number of “1s” and “0s” generated during the first cycle are equivalent (at eight each) and the number of “1s” and “0s” generated during the second cycle are also equivalent (at eight each). However, the number of bit differences (Δ) from the first cycle to the second cycle will equal a maximum of sixteen (i.e., Δ=16), which means that all output signal lines to the bus will be switched high-to-low or low-to-high when passing from the first cycle to the second cycle. This high level of switching can lead to unacceptable simultaneous switching noise, even if the total number of “1s” and the total number of “0s” during the first and second cycles is maintained at about an equivalent level.
Accordingly, notwithstanding these conventional techniques for reducing simultaneous switching noise, there continues to be a need for data inversion circuits that can handle high data bandwidths with high degrees of immunity from SSN. There also continues to be a need for data inversion circuits that can operate at high frequency.